1. Field of the Invention
The present invention relates to a method for producing mask patterns for integrated semiconductor circuits which are divided into groups of standard cells, such as gates, flip-flops, shift registers and the like.
2. Description of the Prior Art
In the production of mask patterns for integrated semiconductor circuits it is desired to place the individual cells of the semiconductor circuits in such a way that as small a chip surface as possible will be required. This means that the wiring surface must be made as small as possible. Since the surface requirement of the wiring strongly depends on the arrangement of the cells, care must be taken to locate the cells in a corresponding optimum manner.
The mask patterns are produced while using an automatic drafting device. This drafting device draws the mask patterns which are then used as photo masks during the production of integrated semiconductor circuits, after having been decreased in size.
Heretofore, branch-and-bound algorithms, have been used as an aid in determining wiring paths. Connection lines have also been laid out in accordance with methods described by Kerninghan, Schweikert and Persky in their essay "An Optimum Channel-Routing Algorithm For Polycell Layouts Of Integrated Circuits", Proc. 10th Design Automation Workshop (1973), Pages 50-59, and Hashimoto and Stevens in their essay "Wire Routing By Optimizing Channel Assignment Within Large Apertures", Proc. 8th Design Automation Workshop (1971) Pages 155-169, each of these publications being fully incorporated herein by this reference.